公开(公告)号：US20210057419A1

公开(公告)日：2021-02-25

申请号：US16833919

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

公开(公告)号：US20190122919A1

公开(公告)日：2019-04-25

申请号：US15984524

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISEOK HONG ,  CHAN-SIC YOON ,  ILYOUNG MOON ,  JEMIN PARK ,  KISEOK LEE ,  JUNG-HOON HAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US20180122811A1

公开(公告)日：2018-05-03

申请号：US15614077

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEIK KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  BONG-SOO KIM ,  JEMIN PARK ,  CHAN-SIC YOON ,  YOOSANG HWANG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.

公开(公告)号：US20250016979A1

公开(公告)日：2025-01-09

申请号：US18616352

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGMIN KIM ,  CHANSIC YOON ,  KISEOK LEE

IPC: H10B12/00

Abstract: A semiconductor device may include first and second active patterns, first and second gate structures, a source/drain layer, a bit line structure, a contact plug structure, and a capacitor. The first and second active patterns are on a cell region and a peripheral circuit region of a substrate, respectively. The first gate structure extends through an upper portion of the first active pattern. The second gate structure is on an upper surface and an upper sidewall of the second active pattern. The source/drain layer is on a portion of the second active pattern that is adjacent to the second gate structure. The bit line structure is on a central portion of the first active pattern, and overlaps the second gate structure in a horizontal direction. The contact plug structure is on opposing end portions of the first active pattern. The capacitor is on the contact plug structure.

公开(公告)号：US20230389289A1

公开(公告)日：2023-11-30

申请号：US18171171

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKHAN PARK ,  KISEOK LEE ,  SEOKHO SHIN ,  HYUNGEUN CHOI ,  BOWON YOO

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/05

Abstract: A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.

公开(公告)号：US20220375941A1

公开(公告)日：2022-11-24

申请号：US17574666

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  HUI-JUNG KIM ,  MIN HEE CHO

IPC: H01L27/108 ,  H01L29/786

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

公开(公告)号：US20190252386A1

公开(公告)日：2019-08-15

申请号：US16268748

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/10805 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20240349492A1

公开(公告)日：2024-10-17

申请号：US18543279

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.

公开(公告)号：US20240324186A1

公开(公告)日：2024-09-26

申请号：US18405026

申请日：2024-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  Chansic YOON

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor device includes active patterns on a substrate, gate structures in recesses of the active patterns and extending in the first direction, first contact plugs electrically connected to opposite edge portions of each of the active patterns, respectively, the first contact plugs being spaced apart from each other in each of the first and second directions and aligned in each of the first and second directions, first insulation spacers surrounding sidewalls of the first contact plugs, the first insulation spacers filling spaces between the first contact plugs in the second direction, a bit line structure filling an opening extending in the second direction between the first insulation spacers, the bit line structure contacting central portions of the active patterns, and a capacitor electrically connected to each of the first contact plugs.

公开(公告)号：US20230309289A1

公开(公告)日：2023-09-28

申请号：US18094719

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun CHOI ,  KISEOK LEE ,  HAEJOON LEE ,  SEUNGJAE JUNG

IPC: H10B80/00 ,  H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50 ,  H10B80/00

Abstract: A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.