公开(公告)号：US20250048628A1

公开(公告)日：2025-02-06

申请号：US18437604

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONYOUNG KWON ,  JIYOUNG KIM ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a peripheral circuit structure on a peripheral substrate, a stack structure that includes a plurality of gate electrodes stacked on the peripheral circuit structure, an n-doped pattern on the stack structure, a vertical structure that extends through the stack structure into the n-doped pattern, a p-doped pattern on the n-doped pattern, and an undoped pattern between the n-doped pattern and then p-doped pattern. The p-doped pattern includes a p-doped horizontal pattern on the undoped pattern, and a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.

公开(公告)号：US20210143154A1

公开(公告)日：2021-05-13

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20210375764A1

公开(公告)日：2021-12-02

申请号：US17399043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108 ,  H01L21/768

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US20210118890A1

公开(公告)日：2021-04-22

申请号：US17137684

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US20190252386A1

公开(公告)日：2019-08-15

申请号：US16268748

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/10805 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20180174971A1

公开(公告)日：2018-06-21

申请号：US15706655

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

IPC: H01L23/532 ,  H01L27/108 ,  H01L27/02

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US20250151279A1

公开(公告)日：2025-05-08

申请号：US18668971

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JIYOUNG KIM ,  IK-HYUNG JOO ,  SUKKANG SUNG ,  SEHOON LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor disposed on the semiconductor substrate. The first transistor includes an insulation structure disposed on the semiconductor substrate, a channel region disposed on the insulation structure and including a first semiconductor layer, and extending in a direction crossing the semiconductor substrate, first source and drain regions electrically connected to the channel region, a first gate insulating layer disposed on the channel region, and a first gate electrode disposed on the first gate insulating layer. A first region that is one of the first source and drain regions and a second region that is another one of the first source and drain regions include different materials or have different crystal structures.

公开(公告)号：US20200083229A1

公开(公告)日：2020-03-12

申请号：US16520730

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIYOUNG KIM ,  DAEWON KIM ,  DONGJIN LEE

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4091

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US20200006231A1

公开(公告)日：2020-01-02

申请号：US16561008

申请日：2019-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US20220246556A1

公开(公告)日：2022-08-04

申请号：US17496488

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin AHN ,  BYUNGJUN KANG ,  JIYOUNG KIM ,  HAE SEOK PARK ,  CHULSOON CHANG

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.