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    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210375764A1

    公开(公告)日：2021-12-02

    申请号：US17399043

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108 ,  H01L21/768

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180174971A1

    公开(公告)日：2018-06-21

    申请号：US15706655

    申请日：2017-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/108 ,  H01L27/02

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200006231A1

    公开(公告)日：2020-01-02

    申请号：US16561008

    申请日：2019-09-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190164975A1

    公开(公告)日：2019-05-30

    申请号：US16108786

    申请日：2018-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNGWOO SONG ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

    IPC: H01L27/108 ,  H01L23/532 ,  H01L29/06

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

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