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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200006231A1

    公开(公告)日：2020-01-02

    申请号：US16561008

    申请日：2019-09-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220399346A1

    公开(公告)日：2022-12-15

    申请号：US17821331

    申请日：2022-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN A KIM ,  SUN YOUNG LEE ,  YONG KWAN KIM ,  JI YOUNG KIM ,  CHANG HYUN CHO

    IPC: H01L27/108 ,  H01L21/66

    Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250040127A1

    公开(公告)日：2025-01-30

    申请号：US18910359

    申请日：2024-10-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN A KIM ,  SUN YOUNG LEE ,  YONG KWAN KIM ,  JI YOUNG KIM ,  CHANG HYUN CHO

    IPC: H10B12/00 ,  H01L21/66

    Abstract: A method of fabricating a semiconductor device. A cell area and a core area are defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180174971A1

    公开(公告)日：2018-06-21

    申请号：US15706655

    申请日：2017-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/108 ,  H01L27/02

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210375764A1

    公开(公告)日：2021-12-02

    申请号：US17399043

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNGWOO SONG ,  Ye-Ro LEE ,  Kwangtae HWANG ,  Kwangmin KIM ,  YONG KWAN KIM ,  JIYOUNG KIM

    IPC: H01L23/532 ,  H01L27/02 ,  H01L27/108 ,  H01L21/768

    Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20210020495A1

    公开(公告)日：2021-01-21

    申请号：US17039431

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

    IPC: H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

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