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    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240357795A1

    公开(公告)日：2024-10-24

    申请号：US18513011

    申请日：2023-11-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tae Jin PARK ,  Hui-Jung KIM ,  Sang Jae PARK ,  Ki Seok LEE ,  Myeong-Dong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335

    Abstract: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230262967A1

    公开(公告)日：2023-08-17

    申请号：US18048561

    申请日：2022-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Hyeok AHN ,  Sung Woo Kim ,  Myeong-Dong LEE ,  Min Ho CHOI

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10897 ,  G11C5/063 ,  H01L27/10814

    Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region along a periphery of the cell region; a cell region isolation layer along the periphery of the cell region in the substrate and defining the cell region; a cell conductive line on the cell region and including a sidewall on the cell region isolation layer; a peripheral gate conductive layer on the peripheral region and including a sidewall on the cell region isolation layer; and an isolation insulating layer in contact with the sidewall of the cell conductive line and the sidewall of the peripheral gate conductive layer on the cell region isolation layer.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240306377A1

    公开(公告)日：2024-09-12

    申请号：US18488229

    申请日：2023-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin KIM ,  Kiseok LEE ,  Seung-Bo KO ,  Chan-Sic YOON ,  Myeong-Dong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/01 ,  H10B12/315

    Abstract: A semiconductor device including a first active pattern and a second active pattern each extending along a first direction and arranged along a second direction intersecting the first direction each of the first and second active patterns including a central part, a first edge part, and a second edge part, a storage node pad on the first edge part of the first active pattern, and a bit-line node contact on the central part of the first active pattern, wherein a top surface of the bit-line node contact is located at a higher level than a top surface of the storage node pad may be provided.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320076A1

    公开(公告)日：2023-10-05

    申请号：US17983489

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., LTD.

    Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10814 ,  G11C5/063

    Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

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