公开(公告)号：US20250054916A1

公开(公告)日：2025-02-13

申请号：US18931874

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Jeonil LEE ,  Jongmin LEE ,  Juik LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US20170125283A1

公开(公告)日：2017-05-04

申请号：US15334469

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20240290677A1

公开(公告)日：2024-08-29

申请号：US18459111

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Joongwon SHIN ,  Jong-Min LEE ,  Jimin CHOI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/53295 ,  H01L24/13 ,  H01L23/291 ,  H01L24/05 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

公开(公告)号：US20230078980A1

公开(公告)日：2023-03-16

申请号：US17696989

申请日：2022-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jeonil LEE ,  Jongmin LEE ,  Juik LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US20230076238A1

公开(公告)日：2023-03-09

申请号：US17882748

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyung KIM ,  Jong-Min LEE ,  Minjung CHOI ,  Jimin CHOI

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/822 ,  H01L25/065 ,  H01L21/66

Abstract: Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.

公开(公告)号：US20240332228A1

公开(公告)日：2024-10-03

申请号：US18535351

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon SHIN ,  Yeonjin LEE ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02206 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/16145

Abstract: A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.

公开(公告)号：US20240113077A1

公开(公告)日：2024-04-04

申请号：US18230768

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nara LEE ,  Yeonjin LEE ,  Jimin CHOI ,  Jongmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

公开(公告)号：US20220326301A1

公开(公告)日：2022-10-13

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Yeonjin LEE ,  Minjung CHOI ,  Jimin CHOI

IPC: G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US20220285189A1

公开(公告)日：2022-09-08

申请号：US17493198

申请日：2021-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjune BAE ,  Jimin CHOI ,  Hyungsik UM ,  Jeongjae BANG ,  Hyeonhui CHO

IPC: H01L21/677 ,  F16C35/00 ,  B66C9/04 ,  B61B12/02 ,  B61B3/02

Abstract: A steering device for an OHT according to some example embodiments of the present inventive concepts includes: an LM block; a steering plate fixedly installed to the LM block and provided with an insertion groove; a link installed in the insertion groove of the steering plate and tilted; a main bearing having an outer circumferential surface in contact with the link to reduce friction when the link is tilted; and a guide roller rotatably installed on a protrusion protruding from the link.

公开(公告)号：US20190157133A1

公开(公告)日：2019-05-23

申请号：US16238172

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/108 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.