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    SEMICONDUCTOR DEVICES
    1.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220085026A1

    公开(公告)日：2022-03-17

    申请号：US17229942

    申请日：2021-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYOSUB KIM ,  KEUNNAM KIM ,  MANBOK KIM ,  SOOJEONG KIM ,  CHULKWON PARK ,  SEUNGBAE JEON ,  YOOSANG HWANG

    IPC: H01L27/108

    Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240349492A1

    公开(公告)日：2024-10-17

    申请号：US18543279

    申请日：2023-12-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20210020495A1

    公开(公告)日：2021-01-21

    申请号：US17039431

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

    IPC: H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

    SEMICONDUCTOR DEVICES
    4.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240306374A1

    公开(公告)日：2024-09-12

    申请号：US18414655

    申请日：2024-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

    Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230397430A1

    公开(公告)日：2023-12-07

    申请号：US18303854

    申请日：2023-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KISEOK LEE ,  KEUNNAM KIM ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  KYUNGHWAN LEE

    IPC: H10B51/30 ,  H10B51/20

    CPC classification number: H10B51/30 ,  H10B51/20

    Abstract: A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE 审中-公开

    公开(公告)号：US20230389310A1

    公开(公告)日：2023-11-30

    申请号：US17994175

    申请日：2022-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUNNAM KIM ,  KISEOK LEE ,  BYEONGJOO KU

    IPC: H10B41/40 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/40 ,  H10B43/20 ,  H01L23/528

    CPC classification number: H01L27/11526 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11578 ,  H01L23/5283

    Abstract: A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.

    VARIABLE RESISTANCE MEMORY DEVICE
    10.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 有权

    公开(公告)号：US20210159277A1

    公开(公告)日：2021-05-27

    申请号：US17167851

    申请日：2021-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

    IPC: H01L27/24 ,  H01L45/00

    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

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