公开(公告)号：US20230253315A1

公开(公告)日：2023-08-10

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  KEUNNAM KIM ,  SOHYUN PARK ,  JIN-HWAN CHUN ,  WOOYOUNG CHOI ,  SUNGHEE HAN ,  INKYOUNG HEO ,  YOOSANG HWANG

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L29/0649 ,  G11C5/10 ,  H01L29/4236 ,  H01L21/76831 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20210296321A1

公开(公告)日：2021-09-23

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INKYOUNG HEO ,  HYO-SUB KIM ,  SOHYUN PARK ,  TAEJIN PARK ,  SEUNG-HEON LEE ,  YOUN-SEOK CHOI ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.