公开(公告)号：US20240349492A1

公开(公告)日：2024-10-17

申请号：US18543279

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.