公开(公告)号：US20220384449A1

公开(公告)日：2022-12-01

申请号：US17735838

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNJUNG KIM ,  HYO-SUB KIM ,  JAY-BOK CHOI ,  YONGSEOK AHN ,  JUNHYEOK AHN ,  KISEOK LEE ,  MYEONG-DONG LEE ,  YOONYOUNG CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

公开(公告)号：US20190096890A1

公开(公告)日：2019-03-28

申请号：US15945401

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONG-DONG LEE ,  JUN-WON LEE ,  KI SEOK LEE ,  BONG-SOO KIM ,  SEOK HAN PARK ,  SUNG HEE HAN ,  YOO SANG HWANG

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

公开(公告)号：US20240349492A1

公开(公告)日：2024-10-17

申请号：US18543279

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.