公开(公告)号：US20220406791A1

公开(公告)日：2022-12-22

申请号：US17729024

申请日：2022-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNJUNG KIM ,  HYUNYONG KIM ,  Sangho LEE ,  YONGSEOK AHN ,  JAY-BOK CHOI

IPC: H01L27/108

Abstract: Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

公开(公告)号：US20220384449A1

公开(公告)日：2022-12-01

申请号：US17735838

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNJUNG KIM ,  HYO-SUB KIM ,  JAY-BOK CHOI ,  YONGSEOK AHN ,  JUNHYEOK AHN ,  KISEOK LEE ,  MYEONG-DONG LEE ,  YOONYOUNG CHOI

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

公开(公告)号：US20220352178A1

公开(公告)日：2022-11-03

申请号：US17547306

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNJUNG KIM ,  HYEWON KIM ,  SEI-RYUNG CHOI

IPC: H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.