公开(公告)号：US20210305115A1

公开(公告)日：2021-09-30

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung CHOI ,  Jung-Hoon HAN ,  Jiho KIM ,  Young-Yong BYUN ,  Yeonjin LEE ,  Jihoon CHANG

IPC: H01L23/31 ,  H01L23/528

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US20240047390A1

公开(公告)日：2024-02-08

申请号：US18377530

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20210280541A1

公开(公告)日：2021-09-09

申请号：US17328365

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20240332228A1

公开(公告)日：2024-10-03

申请号：US18535351

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon SHIN ,  Yeonjin LEE ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02206 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/16145

Abstract: A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.

公开(公告)号：US20240282752A1

公开(公告)日：2024-08-22

申请号：US18509685

申请日：2023-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Yeonjin LEE ,  Jong-Min LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/381

Abstract: Provided is a semiconductor package, including a semiconductor substrate including a plurality of first vias, a chip stack on the semiconductor substrate, the chip stack including first semiconductor chips on the semiconductor substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, and a mold layer on the semiconductor substrate and the chip stack, and exposing a top surface of the chip stack, wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips, wherein the semiconductor substrate further includes lower substrate pads on a bottom surface of the semiconductor substrate, wherein each of the first semiconductor chips includes lower chip pads on a bottom surface of each of the first semiconductor chips, and wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.

公开(公告)号：US20240113077A1

公开(公告)日：2024-04-04

申请号：US18230768

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nara LEE ,  Yeonjin LEE ,  Jimin CHOI ,  Jongmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

公开(公告)号：US20220326301A1

公开(公告)日：2022-10-13

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Yeonjin LEE ,  Minjung CHOI ,  Jimin CHOI

IPC: G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US20210175133A1

公开(公告)日：2021-06-10

申请号：US16898943

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Junyong NOH ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L21/66 ,  H01L21/78

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US20230154876A1

公开(公告)日：2023-05-18

申请号：US18093880

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20230043650A1

公开(公告)日：2023-02-09

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.