公开(公告)号：US20230262967A1

公开(公告)日：2023-08-17

申请号：US18048561

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyeok AHN ,  Sung Woo Kim ,  Myeong-Dong LEE ,  Min Ho CHOI

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10897 ,  G11C5/063 ,  H01L27/10814

Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region along a periphery of the cell region; a cell region isolation layer along the periphery of the cell region in the substrate and defining the cell region; a cell conductive line on the cell region and including a sidewall on the cell region isolation layer; a peripheral gate conductive layer on the peripheral region and including a sidewall on the cell region isolation layer; and an isolation insulating layer in contact with the sidewall of the cell conductive line and the sidewall of the peripheral gate conductive layer on the cell region isolation layer.