公开(公告)号：US20240064964A1

公开(公告)日：2024-02-22

申请号：US18191291

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Min KIM ,  Chan-Sic YOON ,  Jun Hyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate including an active region defined by a device isolation layer, a bit line which is disposed on the substrate and extends in a first direction, a bit line contact which is disposed between the bit line and the substrate and connects the bit line to the active region, a bit line spacer which extends along a sidewall of the bit line, and a bit line contact spacer which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line.

公开(公告)号：US20230262967A1

公开(公告)日：2023-08-17

申请号：US18048561

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyeok AHN ,  Sung Woo Kim ,  Myeong-Dong LEE ,  Min Ho CHOI

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10897 ,  G11C5/063 ,  H01L27/10814

Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region along a periphery of the cell region; a cell region isolation layer along the periphery of the cell region in the substrate and defining the cell region; a cell conductive line on the cell region and including a sidewall on the cell region isolation layer; a peripheral gate conductive layer on the peripheral region and including a sidewall on the cell region isolation layer; and an isolation insulating layer in contact with the sidewall of the cell conductive line and the sidewall of the peripheral gate conductive layer on the cell region isolation layer.