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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250107075A1

    公开(公告)日：2025-03-27

    申请号：US18809859

    申请日：2024-08-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan KIM ,  Joongchan SHIN ,  Hyungeun CHOI ,  Taegyu KANG ,  Keunui KIM ,  Bowon YOO

    IPC: H10B12/00

    Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.

    SEMICONDUCTOR MEMORY DEVICES
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230180456A1

    公开(公告)日：2023-06-08

    申请号：US18059492

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euichul JEONG ,  Kiseok LEE ,  Wonki ROH ,  Hyungeun CHOI

    IPC: H10B12/00

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

    Abstract: A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240421039A1

    公开(公告)日：2024-12-19

    申请号：US18652381

    申请日：2024-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungeun CHOI ,  Kiseok LEE

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: A semiconductor device includes a lower chip structure including a memory structure and a lower wiring structure connected to the memory structure and an upper chip structure on the lower chip structure, where the upper chip structure includes an upper base, peripheral transistors below the upper base, an intermediate wiring structure below the upper base and connected to the peripheral transistors, an upper wiring structure on the upper base, a first through-via penetrating the upper base between the upper wiring structure and the intermediate wiring structure, the first through-via connecting the upper wiring structure and the intermediate wiring structure, and a second through-via extending respectively downward and penetrating the upper base between the upper wiring structure and the lower wiring structure, the second through-via connecting the upper wiring structure and the lower wiring structure.

    SEMICONDUCTOR DEVICE
    7.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230320066A1

    公开(公告)日：2023-10-05

    申请号：US17951379

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moonyoung JEONG ,  Kiseok LEE ,  Hyungeun CHOI ,  Hyungjun NOH ,  Sangho LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10805

    Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230309289A1

    公开(公告)日：2023-09-28

    申请号：US18094719

    申请日：2023-01-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungeun CHOI ,  KISEOK LEE ,  HAEJOON LEE ,  SEUNGJAE JUNG

    IPC: H10B80/00 ,  H10B12/00

    CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50 ,  H10B80/00

    Abstract: A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220173106A1

    公开(公告)日：2022-06-02

    申请号：US17369320

    申请日：2021-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungeun CHOI ,  Kiseok LEE ,  Seungjae JUNG ,  Joongchan SHIN ,  Taehyun AN ,  Moonyoung JEONG ,  Sangyeon HAN

    IPC: H01L27/108 ,  H01L29/08

    Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240431122A1

    公开(公告)日：2024-12-26

    申请号：US18623732

    申请日：2024-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Incheol NAM

    IPC: H10B80/00 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

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