公开(公告)号：US20210183862A1

公开(公告)日：2021-06-17

申请号：US17038355

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon SON ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Seungjae JUNG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US20220359530A1

公开(公告)日：2022-11-10

申请号：US17874512

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji SONG ,  Jaehoon KIM ,  Kwangho PARK ,  Yonghoon SON ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US20210143156A1

公开(公告)日：2021-05-13

申请号：US16916366

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji SONG ,  Jaehoon KIM ,  Kwangho PARK ,  Yonghoon SON ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US20230195172A1

公开(公告)日：2023-06-22

申请号：US18110564

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae JUNG ,  Jeongeun Kim ,  Sanghoon Han ,  Byungsun Kim ,  Dongjun Oh

IPC: G06F1/16

CPC classification number: G06F1/1652 ,  G06F1/1626

Abstract: An electronic device includes a display, a housing, a glass panel provided on the display, and a shielding printed layer provided on a second surface of the glass panel in a region corresponding to a space between a side face of the electronic device and an edge of the display. The glass panel includes a flat portion and a curved portion, which includes a first region having a curvature of the curved portion, a second region perpendicular to the first region and covered by the shielding printed layer, and a chamfer region constructed between the first region and the second region. A ratio of a height of the chamfer region with respect to the first region and a length of the chamfer region with respect to the second region has a value in a range of 2 to 4.

公开(公告)号：US20230005948A1

公开(公告)日：2023-01-05

申请号：US17940441

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US20230031207A1

公开(公告)日：2023-02-02

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Seungjae JUNG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US20210125991A1

公开(公告)日：2021-04-29

申请号：US16923572

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US20210082941A1

公开(公告)日：2021-03-18

申请号：US16857507

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US20240152185A1

公开(公告)日：2024-05-09

申请号：US18414713

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae JUNG ,  Jeongeun Kim ,  Sanghoon Han ,  Byungsun Kim ,  Dongjun Oh

IPC: G06F1/16

CPC classification number: G06F1/1652 ,  G06F1/1626

Abstract: An electronic device includes a display, a housing, a glass panel provided on the display, and a shielding printed layer provided on a second surface of the glass panel in a region corresponding to a space between a side face of the electronic device and an edge of the display. The glass panel includes a flat portion and a curved portion, which includes a first region having a curvature of the curved portion, a second region perpendicular to the first region and covered by the shielding printed layer, and a chamfer region constructed between the first region and the second region. A ratio of a height of the chamfer region with respect to the first region and a length of the chamfer region with respect to the second region has a value in a range of 2 to 4.

公开(公告)号：US20220254783A1

公开(公告)日：2022-08-11

申请号：US17731611

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.