公开(公告)号：US20230005948A1

公开(公告)日：2023-01-05

申请号：US17940441

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US20230031207A1

公开(公告)日：2023-02-02

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Seungjae JUNG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US20210082941A1

公开(公告)日：2021-03-18

申请号：US16857507

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.