公开(公告)号：US20250142810A1

公开(公告)日：2025-05-01

申请号：US18675285

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN KIM ,  HYUNGEUN CHOI ,  TAEJIN PARK ,  EUIJOONG SHIN ,  SANGHO LEE

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device includes a bit line extending above a substrate in a second horizontal direction, first and second active patterns beneath the bit line, each of the first and second active patterns having a first surface in contact with the bit line without a dopant source layer therebetween and a second surface opposite to the first surface in a vertical direction, a back-gate electrode between the first and second active patterns and extending above the substrate in a first horizontal direction by crossing the bit line, a first word line extending in the first horizontal direction at one side of the first active pattern, a second word line extending in the first horizontal direction at an opposite side of the second active pattern, and contact patterns in contact with the second surfaces of the first and second active patterns.

公开(公告)号：US20210057419A1

公开(公告)日：2021-02-25

申请号：US16833919

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

公开(公告)号：US20230389289A1

公开(公告)日：2023-11-30

申请号：US18171171

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKHAN PARK ,  KISEOK LEE ,  SEOKHO SHIN ,  HYUNGEUN CHOI ,  BOWON YOO

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/05

Abstract: A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.