公开(公告)号：US20210005509A1

公开(公告)日：2021-01-07

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISEOK HONG ,  CHAN-SIC YOON ,  ILYOUNG MOON ,  JEMIN PARK ,  KISEOK LEE ,  JUNG-HOON HAN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US20190122919A1

公开(公告)日：2019-04-25

申请号：US15984524

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JISEOK HONG ,  CHAN-SIC YOON ,  ILYOUNG MOON ,  JEMIN PARK ,  KISEOK LEE ,  JUNG-HOON HAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.