SEMICONDUCTOR DEVICES HAVING MULTI-THRESHOLD VOLTAGE

    公开(公告)号:US20190189767A1

    公开(公告)日:2019-06-20

    申请号:US16042114

    申请日:2018-07-23

    Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

    Semiconductor devices having multi-threshold voltage

    公开(公告)号:US10529817B2

    公开(公告)日:2020-01-07

    申请号:US16042114

    申请日:2018-07-23

    Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

    Electronic apparatus and control method thereof

    公开(公告)号:US11568303B2

    公开(公告)日:2023-01-31

    申请号:US16153135

    申请日:2018-10-05

    Abstract: An electronic apparatus is provided. The electronic apparatus includes a first memory configured to store a first artificial intelligence (AI) model including a plurality of first elements and a processor configured to include a second memory. The second memory is configured to store a second AI model including a plurality of second elements. The processor is configured to acquire output data from input data based on the second AI model. The first AI model is trained through an AI algorithm. Each of the plurality of second elements includes at least one higher bit of a plurality of bits included in a respective one of the plurality of first elements.

    Light source module and backlight assembly having the same

    公开(公告)号:US10509159B2

    公开(公告)日:2019-12-17

    申请号:US15407641

    申请日:2017-01-17

    Abstract: A light source module according to some example embodiments includes a first substrate and a plurality of second substrates. The first substrate includes a plurality of connectors configured to at least receive a supply of electrical power and a plurality of first connection pads that are configured to be electrically connected to the plurality of connectors. The second substrates each include a plurality of mounting elements on an upper surface and a plurality of second connection pads on a lower surface of the second substrate and configured to be electrically connected to the plurality of mounting elements. Each mounting element may be connected to a separate light-emitting device. A plurality of connection members may electrically connect the first connection pads of the first substrate to the plurality of second connection pads of the plurality of second substrates.

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