公开(公告)号：US10991574B2

公开(公告)日：2021-04-27

申请号：US16407700

申请日：2019-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L21/285 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US12074023B2

公开(公告)日：2024-08-27

申请号：US18306463

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/0228 ,  C23C16/045 ,  H01L21/02274 ,  H01L21/02296 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/76843 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US11043553B2

公开(公告)日：2021-06-22

申请号：US16520912

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-soo Kim ,  Seung-min Ryu ,  Chang-su Woo ,  Hyung-suk Jung ,  Kyu-ho Cho ,  Youn-joung Cho

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/108

Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

公开(公告)号：US20190189767A1

公开(公告)日：2019-06-20

申请号：US16042114

申请日：2018-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol SONG ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

公开(公告)号：US11682555B2

公开(公告)日：2023-06-20

申请号：US17224365

申请日：2021-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L21/0228 ,  C23C16/045 ,  H01L21/0262 ,  H01L21/02274 ,  H01L21/02296 ,  H01L21/28556 ,  H01L21/76843 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US11929389B2

公开(公告)日：2024-03-12

申请号：US17324492

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-soo Kim ,  Seung-min Ryu ,  Chang-su Woo ,  Hyung-suk Jung ,  Kyu-ho Cho ,  Youn-joung Cho

IPC: H01L21/28 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/40 ,  H10B12/315

Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

公开(公告)号：US11588012B2

公开(公告)日：2023-02-21

申请号：US17200081

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-goo Kang ,  Sang-yeol Kang ,  Youn-soo Kim ,  Jin-su Lee ,  Hyung-suk Jung ,  Kyu-ho Cho

IPC: H01L49/02 ,  H01L21/285 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/02 ,  H01L21/321 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

公开(公告)号：US20200091275A1

公开(公告)日：2020-03-19

申请号：US16520912

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-soo Kim ,  Seung-min Ryu ,  Chang-su Woo ,  Hyung-suk Jung ,  Kyu-ho Cho ,  Youn-joung Cho

IPC: H01L49/02 ,  H01L27/108

Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

公开(公告)号：US20190355806A1

公开(公告)日：2019-11-21

申请号：US16273603

申请日：2019-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-goo KANG ,  Sang-yeol Kang ,  Youn-soo Kim ,  Jin-su Lee ,  Hyung-suk Jung ,  Kyu-ho CHO

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/02 ,  H01L27/108 ,  H01L21/321 ,  C23C16/40 ,  C23C16/56 ,  C23C16/455

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

公开(公告)号：US20160020324A1

公开(公告)日：2016-01-21

申请号：US14573429

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Kwi Park ,  Koung-Min Ryu ,  Moon-Han Park ,  Hyung-suk Jung ,  Jong-hoon Baek ,  Su-Young Choi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.

Abstract translation: 半导体器件包括应力源和绝缘图案。 形成器件隔离层以限定衬底上的有源区。 在有源区上形成第一栅电极。 在器件隔离层上形成第二栅电极。 在第一栅极电极和第二栅极电极之间的有源区域中形成沟槽。 在沟槽中形成应力源。 设置在应力器和器件隔离层之间并与第二栅电极相邻的空腔。 在空腔中形成绝缘图案。