公开(公告)号：US12074023B2

公开(公告)日：2024-08-27

申请号：US18306463

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/0228 ,  C23C16/045 ,  H01L21/02274 ,  H01L21/02296 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/76843 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US10355073B2

公开(公告)日：2019-07-16

申请号：US15448683

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-suk Lee ,  Ji-won Yu ,  Ji-woon Park

IPC: H01L49/02 ,  H01L23/535 ,  H01L27/108

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

公开(公告)号：US11064603B2

公开(公告)日：2021-07-13

申请号：US16270874

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-woon Park ,  Jin-an Lee

IPC: H05K1/02 ,  H01L25/18 ,  H01L23/538 ,  H01L23/66 ,  H05K1/18

Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

公开(公告)号：US10991574B2

公开(公告)日：2021-04-27

申请号：US16407700

申请日：2019-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L21/285 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US11682555B2

公开(公告)日：2023-06-20

申请号：US17224365

申请日：2021-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon Park ,  Jin-su Lee ,  Hyung-suk Jung

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L21/0228 ,  C23C16/045 ,  H01L21/0262 ,  H01L21/02274 ,  H01L21/02296 ,  H01L21/28556 ,  H01L21/76843 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US11670673B2

公开(公告)日：2023-06-06

申请号：US17147542

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-suk Lee ,  Ji-won Yu ,  Ji-woon Park

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/10

CPC classification number: H01L28/75 ,  H01L27/101 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10852 ,  H01L27/10855

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

公开(公告)号：US10903308B2

公开(公告)日：2021-01-26

申请号：US16508695

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-suk Lee ,  Ji-won Yu ,  Ji-woon Park

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/10

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

公开(公告)号：US10373831B2

公开(公告)日：2019-08-06

申请号：US15651068

申请日：2017-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-won Yu ,  Hyun-suk Lee ,  Ji-woon Park ,  Gi-hee Cho ,  Hee-sook Park ,  Woong-hee Sohn

IPC: C23C16/455 ,  H01L21/205 ,  H01L21/54 ,  H01L21/67 ,  H01L21/677 ,  C23C16/04 ,  C23C16/44

Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.