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    Semiconductor devices having multi-threshold voltage
    2.
    发明授权
    Semiconductor devices having multi-threshold voltage 有权

    公开(公告)号：US10529817B2

    公开(公告)日：2020-01-07

    申请号：US16042114

    申请日：2018-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-yeol Song ,  Wan-don Kim ,  Su-young Bae ,  Dong-soo Lee ,  Jong-han Lee ,  Hyung-suk Jung ,  Sang-jin Hyun

    IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51

    Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

    Methods of manufacturing integrated circuit devices having a fin-type active region
    3.
    发明授权
    Methods of manufacturing integrated circuit devices having a fin-type active region 有权

    公开(公告)号：US10593670B2

    公开(公告)日：2020-03-17

    申请号：US15697720

    申请日：2017-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo Na

    IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

    Fin-type field effect transistors including aluminum doped metal-containing layer
    5.
    发明授权
    Fin-type field effect transistors including aluminum doped metal-containing layer 有权
    鳍型场效应晶体管，包括掺杂铝的金属层

    公开(公告)号：US09240483B2

    公开(公告)日：2016-01-19

    申请号：US13684655

    申请日：2012-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： June-hee Lee ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

    IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/785 ,  H01L27/0886

    Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

    Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。

    FIN-TYPE FIELD EFFECT TRANSISTORS INCLUDING ALUMINUM DOPED METAL-CONTAINING LAYER
    6.
    发明申请
    FIN-TYPE FIELD EFFECT TRANSISTORS INCLUDING ALUMINUM DOPED METAL-CONTAINING LAYER 有权
    包含铝金属含金属层的FIN型场效应晶体管

    公开(公告)号：US20130277748A1

    公开(公告)日：2013-10-24

    申请号：US13684655

    申请日：2012-11-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： June-Hee LEE ,  Jae-yeol Song ,  Hye-Ian Lee ,  Hong-bae Park ,  Sang-jin Hyun

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L27/0886

    Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

    Abstract translation: 半导体器件包括鳍型有源区; 覆盖所述鳍状有源区的上表面和相对的侧表面的栅介电层; 以及在所述栅极电介质层上延伸以覆盖所述鳍状有源区的上表面和相对的侧表面并跨越所述鳍型有源区的栅极线。 栅极线包括铝（Al）掺杂的含金属层，其延伸以覆盖翅片型有源区的上表面和相对的侧表面至均匀的厚度;以及间隙填充金属层，其在Al掺杂的金属 - 在翅片型有源区域上方。 还描述了相关的制造方法。

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