公开(公告)号：US10313426B2

公开(公告)日：2019-06-04

申请号：US14486227

申请日：2014-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-in Kim ,  Ji-hwan Seo ,  Jin-wook Lee

IPC: G06F3/0481 ,  H04L29/08 ,  H04W4/50 ,  H04W4/80

Abstract: A method of managing a control right in a 1:n network topology is provided. The master device includes a display unit configured to display a first screen, a control unit configured to receive a request for at least one right for controlling the master device and/or a mirroring service from at least one of a plurality of client devices mirroring the first screen, and to grant the requested right to the at least one of the plurality of client devices in response to the request, and a communication unit configured to receive the request and to transmit the response.

公开(公告)号：US20200168720A1

公开(公告)日：2020-05-28

申请号：US16552150

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US10651179B2

公开(公告)日：2020-05-12

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US09520726B2

公开(公告)日：2016-12-13

申请号：US14272116

申请日：2014-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jee-eun Yang ,  Jin-wook Lee ,  Sung-young Yun

IPC: H02J7/00 ,  H02N2/18 ,  H01L41/113

CPC classification number: H02J7/0042 ,  H01L41/1136 ,  H02J7/0052 ,  H02J2007/0059 ,  H02N2/186

Abstract: An auxiliary device including an energy harvester and an electronic device including the auxiliary device are provided. The auxiliary device includes: a housing; a storage module which is moveable within the housing; and at least one piezoelectric transducer which disposed in the housing, such that a motion of the storage module causes a deformation of the piezoelectric transducer, thus generating electric energy. An end of the piezoelectric transducer may be fixedly connected to the storage module.

Abstract translation: 提供了包括能量收集器和包括辅助装置的电子装置的辅助装置。 辅助装置包括：壳体; 存储模块，其可在所述壳体内移动; 以及设置在壳体中的至少一个压电换能器，使得存储模块的运动导致压电换能器的变形，从而产生电能。 压电换能器的端部可以固定地连接到存储模块。

公开(公告)号：US12015063B2

公开(公告)日：2024-06-18

申请号：US17707036

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon Lee ,  Jin-wook Lee ,  Min-chan Gwak ,  Kye-Hyun Baek ,  Hong-bae Park

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US11955531B2

公开(公告)日：2024-04-09

申请号：US18174902

申请日：2023-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66515 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US10304840B2

公开(公告)日：2019-05-28

申请号：US15084785

申请日：2016-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-hee Bai ,  Myeong-cheol Kim ,  Kwan-heum Lee ,  Do-hyoung Kim ,  Jin-wook Lee ,  Seung-mo Ha ,  Dong-Hoon Khang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

公开(公告)号：US10115797B2

公开(公告)日：2018-10-30

申请号：US15059673

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Sang-Jin Hyun ,  Jin-wook Lee ,  Kee-sang Kwon ,  Ki-hyung Ko ,  Sung-woo Myung

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/28

Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

公开(公告)号：US11626503B2

公开(公告)日：2023-04-11

申请号：US17393217

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-young Kwak ,  Ji-ye Kim ,  Jung-hwan Chun ,  Min-chan Gwak ,  Dong-hyun Roh ,  Jin-wook Lee ,  Sang-jin Hyun

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/45

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

公开(公告)号：US11309393B2

公开(公告)日：2022-04-19

申请号：US16404857

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon Lee ,  Jin-wook Lee ,  Min-chan Gwak ,  Kye-Hyun Baek ,  Hong-bae Park

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.