公开(公告)号：US10134663B2

公开(公告)日：2018-11-20

申请号：US15714801

申请日：2017-09-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

公开(公告)号：US10037966B2

公开(公告)日：2018-07-31

申请号：US15375072

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro Iwasaki ,  Takeumi Kato ,  Takanori Okita ,  Yoshikazu Shimote ,  Shinji Baba ,  Kazuyuki Nakagawa ,  Michitaka Kimura

IPC: H01L23/00 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L21/48 ,  H01L21/56 ,  H01L25/075

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/056 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/1605 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75745 ,  H01L2224/75824 ,  H01L2224/8101 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/81201 ,  H01L2924/00

Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.

公开(公告)号：US09171814B2

公开(公告)日：2015-10-27

申请号：US14645289

申请日：2015-03-11

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

公开(公告)号：US09818679B2

公开(公告)日：2017-11-14

申请号：US14871742

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

公开(公告)号：US09171791B2

公开(公告)日：2015-10-27

申请号：US14249097

申请日：2014-04-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Toshihiro Iwasaki ,  Masaki Watanabe

IPC: H01L23/498 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract translation: 本发明提供作为低成本倒装芯片BGA的多引脚半导体器件。 在倒装芯片BGA中，多层布线基板的上表面的周边区域中的多个信号接合电极被分离为内部和外部的多个信号接合电极，并且耦合到多个内部的信号布线耦合的多个信号通孔是 位于多行信号键合电极和多个核心电源用接合电极之间的中心区域，使得可以减小芯片焊盘间距，并且能够在不增加数量的情况下降低BGA的成本 的多层布线基板中的层。

公开(公告)号：US09837369B2

公开(公告)日：2017-12-05

申请号：US15023716

申请日：2013-09-27

Applicant: Renesas Electronics Corporation

Inventor： Yoshikazu Shimote ,  Shinji Baba ,  Toshihiro Iwasaki ,  Kazuyuki Nakagawa

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L21/78 ,  H05K3/28 ,  H05K3/34 ,  H01L21/683

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

公开(公告)号：US20150187720A1

公开(公告)日：2015-07-02

申请号：US14645289

申请日：2015-03-11

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。

公开(公告)号：US08994175B2

公开(公告)日：2015-03-31

申请号：US14139948

申请日：2013-12-24

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。

公开(公告)号：US20140284789A1

公开(公告)日：2014-09-25

申请号：US14139948

申请日：2013-12-24

Applicant: Renesas Electronics Corporation

Inventor： Masaki Watanabe ,  Shinji Baba ,  Muneharu Tokunaga ,  Toshihiro Iwasaki

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

Abstract translation: 以提高半导体器件的倒装芯片接合中的耦合可靠性。 通过在制造半导体器件中使用布线基板，其中布线基板的上表面上穿过阻焊膜的开口区域的布线在布线的一侧上具有凸块电极， 另一方面，在其上没有凸起电极的多个宽幅部分上，在焊料预涂工序的回流处理期间，布线上的焊料可以分散到每个宽幅部分。 通过这样的结构，能够减少各宽端部的端子上的焊料和焊料之间的高度差，并且提高倒装芯片接合时的耦合可靠性。