公开(公告)号：US20170271250A1

公开(公告)日：2017-09-21

申请号：US15613333

申请日：2017-06-05

Applicant: MEDIATEK Inc.

Inventor： Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.

公开(公告)号：US20190051609A1

公开(公告)日：2019-02-14

申请号：US16163614

申请日：2018-10-18

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20170338175A1

公开(公告)日：2017-11-23

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US20180033774A1

公开(公告)日：2018-02-01

申请号：US15726471

申请日：2017-10-06

Applicant: MediaTek Inc

Inventor： Che-Hung KUO ,  Ying-Chih CHEN ,  Che-Ya CHOU

IPC: H01L25/065 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48265 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

公开(公告)号：US20170084589A1

公开(公告)日：2017-03-23

申请号：US15203444

申请日：2016-07-06

Applicant: MediaTek Inc.

Inventor： Che-Hung KUO ,  Che-Ya CHOU

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.

公开(公告)号：US20160260659A1

公开(公告)日：2016-09-08

申请号：US15048807

申请日：2016-02-19

Applicant: MediaTek Inc.

Inventor： Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括再分配层（RDL）结构裸片附着表面和与裸片附着表面相对的凸起附着表面。 半导体管芯安装在再分配层（RDL）结构的管芯附接表面上。 第一焊料掩模层设置在裸片附着表面上。 第一焊料掩模层围绕半导体管芯。 附加电路结构设置在第一焊料掩模的围绕半导体管芯的部分上。 附加电路结构包括具有第一宽度的焊盘部分和通孔部分具有小于第一宽度的第二宽度。 通孔部分穿过第一焊料掩模层以耦合再分布层（RDL）结构。

公开(公告)号：US20190131233A1

公开(公告)日：2019-05-02

申请号：US16232129

申请日：2018-12-26

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

公开(公告)号：US20180025985A1

公开(公告)日：2018-01-25

申请号：US15498542

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Min-Chen LIN ,  Che-Ya CHOU ,  Nan-Cheng CHEN

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16195 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2924/37001

Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

公开(公告)号：US20170040266A1

公开(公告)日：2017-02-09

申请号：US15331016

申请日：2016-10-21

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Nai-Wei LIU ,  Wei-Che HUANG ,  Che-Ya CHOU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装，其包括具有第一表面和与第一基板相对的第二表面的第一再分布层（RDL）结构。 第一RDL结构包括靠近第一RDL结构的第一表面的多个第一导电迹线。 天线图案靠近第一RDL结构的第二表面设置。 第一半导体管芯设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构设置在第一RDL结构的第一表面上并电耦合到第一RDL结构。 多个导电结构通过第一RDL结构的多个第一导电迹线与天线图案间隔开。

公开(公告)号：US20140042615A1

公开(公告)日：2014-02-13

申请号：US13933259

申请日：2013-07-02

Applicant: MediaTek Inc.

Inventor： Ching-Liou HUANG ,  Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer.

Abstract translation: 提供了一种示例性的倒装芯片封装，其包括：封装结构，其具有形成在其上的第一焊盘和第二焊盘，其中所述第一接合焊盘具有与所述第二接合焊盘的特征尺寸不同的特征尺寸; 面向封装结构的半导体芯片，具有形成在其上的第一下凸块金属（UBM）层和第二下凸块金属（UBM）层，其中第一UBM层具有与第二UBM层的特征尺寸不同的特征尺寸 ; 设置在所述第一接合焊盘和所述第一UBM层之间的第一导电元件; 以及设置在所述第二接合焊盘和所述第二UBM层之间的第二导电元件。