公开(公告)号：US20150357291A1

公开(公告)日：2015-12-10

申请号：US14826471

申请日：2015-08-14

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Liou HUANG ,  Thomas Matthew GREGORICH

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/183 ,  H01L2924/35 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 还包括延伸穿过半导体管芯的边缘的阻焊层。 最后，提供了形成在衬底上并覆盖第一导电迹线和半导体晶粒的模塑料。

公开(公告)号：US20160056105A1

公开(公告)日：2016-02-25

申请号：US14932122

申请日：2015-11-04

Applicant: MediaTek Inc

Inventor： Kuei-Ti CHAN ,  Tzu-Hung LIN ,  Ching-Liou HUANG

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L23/64

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.

Abstract translation: 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 附加的凸块下冶金层设置在与凸块下金属层隔离的第一钝化层上; 以及设置在附加的凸块下金属层上的导电柱。

公开(公告)号：US20160133594A1

公开(公告)日：2016-05-12

申请号：US14535643

申请日：2014-11-07

Applicant: MediaTek Inc.

Inventor： Ching-Liou HUANG ,  Ta-Jen YU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16235 ,  H01L2224/17104 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括具有与器件附着表面相对的器件附着表面和焊球附着表面的基座。 导电通孔设置穿过基座。 导电通孔包括与基座的装置附接表面对准的第一端子表面。 半导体管芯通过导电结构安装在基座上。 导电结构与导电通孔的第一端子表面接触。

公开(公告)号：US20150194403A1

公开(公告)日：2015-07-09

申请号：US14663755

申请日：2015-03-20

Applicant: MediaTek Inc

Inventor： Kuei-Ti CHAN ,  Tzu-Hung LIN ,  Ching-Liou HUANG

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.

Abstract translation: 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 无源器件设置在凸块下金属层上，并且附加的凸块下金属层设置在与凸块下金属层隔离的第一钝化层上。 导电柱设置在另外的凸块下金属层上，其中导电柱和无源器件处于同一水平。

公开(公告)号：US20150348932A1

公开(公告)日：2015-12-03

申请号：US14825443

申请日：2015-08-13

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Liou HUANG ,  Thomas Matthew GREGORICH

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 形成阻焊层，阻焊层的一部分和第一导电性迹线的一部分共同具有T形截面。

公开(公告)号：US20140091481A1

公开(公告)日：2014-04-03

申请号：US14103066

申请日：2013-12-11

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Liou HUANG ,  Thomas Matthew GREGORICH

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 还包括延伸穿过半导体管芯的边缘的阻焊层。 最后，提供填充衬底和半导体管芯之间的间隙的底部填充材料。

公开(公告)号：US20140042615A1

公开(公告)日：2014-02-13

申请号：US13933259

申请日：2013-07-02

Applicant: MediaTek Inc.

Inventor： Ching-Liou HUANG ,  Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer.

Abstract translation: 提供了一种示例性的倒装芯片封装，其包括：封装结构，其具有形成在其上的第一焊盘和第二焊盘，其中所述第一接合焊盘具有与所述第二接合焊盘的特征尺寸不同的特征尺寸; 面向封装结构的半导体芯片，具有形成在其上的第一下凸块金属（UBM）层和第二下凸块金属（UBM）层，其中第一UBM层具有与第二UBM层的特征尺寸不同的特征尺寸 ; 设置在所述第一接合焊盘和所述第一UBM层之间的第一导电元件; 以及设置在所述第二接合焊盘和所述第二UBM层之间的第二导电元件。