公开(公告)号：US12046509B2

公开(公告)日：2024-07-23

申请号：US17128866

申请日：2020-12-21

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Alexander Breymesser ,  Eva-Maria Hof ,  Mathias Plappert ,  Carsten Schaeffer

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/52

CPC classification number: H01L21/76838 ,  H01L23/52 ,  H01L23/564

Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.

公开(公告)号：US20240113216A1

公开(公告)日：2024-04-04

申请号：US18471777

申请日：2023-09-21

Applicant: Infineon Technologies AG

Inventor： Yuliya Lisunova ,  Andreas Frank Behrendt ,  Carsten Schaeffer ,  Simon Paul Sindermann ,  Adriana Mercedes Sanchez Lotero ,  Silke Liebscher

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712

Abstract: Disclosed herein is a power semiconductor device including a semiconductor body, a first load terminal, a second load terminal, an active region, an edge termination region, and a thin film layer that includes a bulk material and a laminar filler compound. Furthermore, a method of producing such a power semiconductor device is described herein, the method including: providing a thin film including a mixture of a bulk material component and a laminar filler compound onto a surface of at least parts of the edge termination region and/or over at least parts of the first load terminal; and curing the obtained mixture of the bulk material and laminar filler compound to generate a thin-film layer that includes a bulk material and a laminar filler compound.

公开(公告)号：US20170162390A1

公开(公告)日：2017-06-08

申请号：US15365627

申请日：2016-11-30

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Jens Peter Konrath ,  Francisco Javier Santos Rodriguez ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Werner Schustereder ,  Guenther Wellenzohn

IPC: H01L21/04 ,  H01L29/47

CPC classification number: H01L29/401 ,  H01L21/02697 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/2258 ,  H01L21/28575 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/45 ,  H01L29/452 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.

公开(公告)号：US09337185B2

公开(公告)日：2016-05-10

申请号：US14561357

申请日：2014-12-05

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Carsten Schaeffer

IPC: H01L21/70 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/47 ,  H01L29/739 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0615 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.

Abstract translation: 半导体器件包括从半导体衬底的主表面延伸到半导体衬底中的第一掺杂区域。 此外，半导体器件包括邻近第一掺杂区布置的第二掺杂区。 第一掺杂区域包括从半导体衬底的主表面延伸到第二掺杂区域的至少一个低掺杂剂量部分。 第一掺杂区域的低掺杂剂量部分内的掺杂剂量小于击穿电荷的3倍。 另外，半导体器件包括与半导体衬底的主表面处的第一掺杂区域接触的第一电极结构。 第一电极结构在半导体衬底的主表面上的功函数大于4.9eV或低于4.4eV。

公开(公告)号：US20230395539A1

公开(公告)日：2023-12-07

申请号：US18235585

申请日：2023-08-18

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/485 ,  H01L23/53219 ,  H01L23/53233

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US20220059477A1

公开(公告)日：2022-02-24

申请号：US17400303

申请日：2021-08-12

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Jens Brandenburg ,  Christoffer Erbert ,  Joachim Hirschler ,  Oliver Humbel ,  Thomas Rupp ,  Carsten Schaeffer ,  Julia Zischang

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/485

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

公开(公告)号：US10777506B2

公开(公告)日：2020-09-15

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US09859395B2

公开(公告)日：2018-01-02

申请号：US14502882

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef-Georg Bauer ,  Carsten Schaeffer ,  Oliver Humbel ,  Angelika Koprowski ,  Sirinpa Monayakul

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78 ,  H01L23/31 ,  H01L21/283 ,  H01L29/47 ,  H01L29/06

CPC classification number: H01L29/66143 ,  H01L21/02115 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/283 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/408 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

公开(公告)号：US20170025408A1

公开(公告)日：2017-01-26

申请号：US15210449

申请日：2016-07-14

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Holger Huesken ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Roman Roth ,  Christian Philipp Sandow ,  Carsten Schaeffer ,  Stephan Voss

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L27/0664 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/205 ,  H01L29/45 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

Abstract translation: 一种半导体器件，包括电连接到半导体器件的第一负载端子（E）的源极区域和包括具有第一带隙的第一半导体材料（M1）的漂移区域，所述漂移区域具有第一导电类型的掺杂剂 并且被配置为在半导体器件的第一负载端子（E）和第二负载端子（C）之间承载至少一部分负载电流。 半导体器件还包括具有与第一导电类型互补的第二导电类型的掺杂剂并且与第一负载端子（E）电连接的半导体本体区域，在半导体主体区域和漂移区域之间形成pn- 其中所述pn结被配置为阻挡施加在所述第一负载端子（E）和所述第二负载端子（C）之间的电压。所述半导体体区域将所述源极区域与所述漂移区域隔离，并且包括减小的带隙区域 包括具有小于所述第一带隙的第二带隙的第二半导体材料（M2），其中所述还原带隙区域布置在所述半导体主体区域中，使得所述还原带隙区域和所述源极区域在 沿着垂直方向（Z）的横截面，沿着第一横向方向（X）的公共横向延伸范围（LR）和公共垂直伸展中的至少一个 离子范围（VR）沿垂直方向（Z）。

公开(公告)号：US09362349B2

公开(公告)日：2016-06-07

申请号：US13923436

申请日：2013-06-21

Applicant: Infineon Technologies AG

Inventor： Dorothea Werber ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Carsten Schaeffer ,  Volodymyr Komarnitskyy ,  Anton Mauder ,  Holger Schulze ,  Gerhard Miller

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/861 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.

Abstract translation: 半导体器件包括具有至少一个器件单元的单元区域，其中至少一个器件单元包括第一导电类型的第一器件区域。 所述半导体器件还包括邻接所述至少一个器件单元的第一器件区域的第二导电类型的漂移区域，与所述漂移区域相邻的所述第一导电类型的掺杂区域以及被配置为减少电荷的电荷载流子寿命降低装置 在第一导电类型的掺杂区域中的载流子寿命。