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公开(公告)号：US12021135B2
公开(公告)日：2024-06-25
申请号：US18314850
申请日：2023-05-10
发明人： Tao Li , Indira Seshadri , Nelson Felix , Eric Miller
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/823814 , H01L21/823885 , H01L27/092 , H01L29/0653 , H01L29/0847 , H01L29/7827
摘要： A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.
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公开(公告)号：US20240105605A1
公开(公告)日：2024-03-28
申请号：US17934913
申请日：2022-09-23
IPC分类号： H01L23/528 , H01L21/8234 , H01L23/48 , H01L23/522
CPC分类号： H01L23/5286 , H01L21/823475 , H01L23/481 , H01L23/5226
摘要： A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.
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公开(公告)号：US20240079276A1
公开(公告)日：2024-03-07
申请号：US17823967
申请日：2022-09-01
发明人： Ruqiang Bao , Effendi Leobandung , Eric Miller , Charlotte DeWan Adams , Cornelius Brown Peethala , Liqiao Qin
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/4908 , H01L29/66439 , H01L29/66742 , H01L29/775 , H01L29/78696
摘要： Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.
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公开(公告)号：US11462631B2
公开(公告)日：2022-10-04
申请号：US16848451
申请日：2020-04-14
发明人： Kangguo Cheng , Eric Miller , Fee Li Lie , Gauri Karve , Marc A. Bergendahl , John Ryan Sporre
摘要： Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.
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公开(公告)号：US10937892B2
公开(公告)日：2021-03-02
申请号：US16127720
申请日：2018-09-11
IPC分类号： H01L29/66 , H01L21/02 , H01L29/417
摘要： A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.
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公开(公告)号：US10535529B2
公开(公告)日：2020-01-14
申请号：US16000485
申请日：2018-06-05
IPC分类号： H01L29/80 , H01L21/308 , H01L21/8234 , H01L29/78 , H01L29/66
摘要： Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.
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公开(公告)号：US11916013B2
公开(公告)日：2024-02-27
申请号：US17465815
申请日：2021-09-02
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76808 , H01L21/76816 , H01L21/76834 , H01L21/76892 , H01L21/76897 , H01L23/5283
摘要： Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.
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公开(公告)号：US11646358B2
公开(公告)日：2023-05-09
申请号：US17728437
申请日：2022-04-25
IPC分类号： H01L29/66 , H01L21/28 , H01L29/49 , H01L29/78 , H01L29/417
CPC分类号： H01L29/66515 , H01L21/28088 , H01L29/41791 , H01L29/4966 , H01L29/6681 , H01L29/7851
摘要： A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.
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公开(公告)号：US11646235B2
公开(公告)日：2023-05-09
申请号：US17382442
申请日：2021-07-22
发明人： Eric Miller , Marc A. Bergendahl , Kangguo Cheng , Sean Teehan , John Sporre
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/66 , H01L29/10 , H01L21/02 , H01L29/78 , H01L27/088 , H01L21/762
CPC分类号： H01L21/823487 , H01L21/02532 , H01L21/02592 , H01L21/823412 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L27/088 , H01L29/0847 , H01L29/1037 , H01L29/6653 , H01L29/6656 , H01L29/66666 , H01L29/7827 , H01L21/76224
摘要： Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.
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公开(公告)号：US20230065078A1
公开(公告)日：2023-03-02
申请号：US17465815
申请日：2021-09-02
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
摘要： Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.
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