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公开(公告)号：US11031250B2
公开(公告)日：2021-06-08
申请号：US16204336
申请日：2018-11-29
IPC分类号： H01L27/088 , H01L21/3105 , H01L29/78 , H01L27/22 , H01L21/311
摘要： A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.
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公开(公告)号：US10937892B2
公开(公告)日：2021-03-02
申请号：US16127720
申请日：2018-09-11
IPC分类号： H01L29/66 , H01L21/02 , H01L29/417
摘要： A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.
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3.发明申请公开(公告)号：US20200020542A1
公开(公告)日：2020-01-16
申请号：US16033384
申请日：2018-07-12
IPC分类号： H01L21/324 , H01L21/768 , H01L21/02 , H01L49/02 , H01L23/522
摘要： A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.
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公开(公告)号：US10177076B2
公开(公告)日：2019-01-08
申请号：US15683322
申请日：2017-08-22
发明人： Griselda Bonilla , Elbert Huang , Son Nguyen , Takeshi Nogami , Christopher J. Penny , Deepika Priyadarshini
IPC分类号： H01L23/482 , H01L29/78 , H01L29/423 , H01L21/8234 , H01L29/786 , H01L27/088 , H01L21/768 , H01L29/66 , H01L29/49
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
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公开(公告)号：US09793193B1
公开(公告)日：2017-10-17
申请号：US15299906
申请日：2016-10-21
发明人： Griselda Bonilla , Elbert Huang , Son Nguyen , Takeshi Nogami , Christopher J. Penny , Deepika Priyadarshini
IPC分类号： H01L23/482 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L23/4821 , H01L21/76805 , H01L21/7682 , H01L21/76895 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823487 , H01L27/088 , H01L29/42392 , H01L29/4991 , H01L29/66666 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
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6.发明公开公开(公告)号：US20240145473A1
公开(公告)日：2024-05-02
申请号：US18050032
申请日：2022-10-26
发明人： Tsung-Sheng Kang , Su Chen Fan , Jingyun Zhang , Ruqiang Bao , Son Nguyen
IPC分类号： H01L27/092 , H01L21/822 , H01L21/8238 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L27/0922 , H01L21/8221 , H01L21/823807 , H01L21/823871 , H01L21/823878 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/775
摘要： A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.
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公开(公告)号：US20240105613A1
公开(公告)日：2024-03-28
申请号：US17954826
申请日：2022-09-28
IPC分类号： H01L23/528 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L23/5286 , H01L29/0673 , H01L29/401 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： A semiconductor device includes a frontside including first metal structures, transistors disposed between the frontside and a backside opposite the frontside, each transistor including a source/drain positioned within a stack of nanolayers, the stack of nanolayers forming a gate structure and a power circuit on the backside and connected to the transistors by backside contacts. A backside dielectric isolation has a horizontal portion along a backside of the gate structure and a vertical portion substantially perpendicular to the backside and self-aligned to selected source/drains to electrically isolate the power circuit from the transistors.
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公开(公告)号：US11791398B2
公开(公告)日：2023-10-17
申请号：US17136169
申请日：2020-12-29
IPC分类号： H01L29/66 , H01L29/417 , H01L21/02
CPC分类号： H01L29/6656 , H01L21/0234 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L29/41775 , H01L29/41791
摘要： A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.
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公开(公告)号：US11171054B2
公开(公告)日：2021-11-09
申请号：US16837075
申请日：2020-04-01
发明人： Son Nguyen , Rudy J. Wojtecki , Noel Arellano , Alexander Edward Hess , Thomas Jasper Haigh, Jr. , Cornelius Brown Peethala , Balasubramanian S. Pranatharthi Haran
IPC分类号： H01L21/768 , H01L21/02 , H01L23/535 , H01L21/311 , H01L23/532 , H01L21/3105
摘要： A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.
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10.发明申请公开(公告)号：US20190333983A1
公开(公告)日：2019-10-31
申请号：US15963406
申请日：2018-04-26
发明人： Joshua M. Rubin , Son Nguyen
IPC分类号： H01L49/02 , H01L21/768
摘要： A semiconductor device includes a base structure including contacts and a first interlevel dielectric (ILD) layer, a metal-insulator metal (MIM) capacitor structure on the base structure, a second ILD layer on the MIM capacitor structure, and a plurality of vias including a first via on a first one of the contacts and penetrating through the first and second ILD layers, first and third etch tuning layers of the MIM capacitor structure and a second plate of the MIM capacitor structure, and a second via on a second one of the contacts and penetrating through the first and second ILD layers, a second etch tuning layer of the MIM capacitor structure, and first and third plates of the MIM capacitor structure.
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