公开(公告)号：US11380589B2

公开(公告)日：2022-07-05

申请号：US16662845

申请日：2019-10-24

Applicant: TESSERA, INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

公开(公告)号：US11276612B2

公开(公告)日：2022-03-15

申请号：US16681347

申请日：2019-11-12

Applicant: TESSERA, INC.

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

公开(公告)号：US20210399114A1

公开(公告)日：2021-12-23

申请号：US17465135

申请日：2021-09-02

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Julien Frougier ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/311 ,  H01L29/775

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

公开(公告)号：US20210335706A1

公开(公告)日：2021-10-28

申请号：US17341112

申请日：2021-06-07

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

公开(公告)号：US20210335619A1

公开(公告)日：2021-10-28

申请号：US17340915

申请日：2021-06-07

Applicant: Tessera, Inc.

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/8234

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US20210305247A1

公开(公告)日：2021-09-30

申请号：US17221401

申请日：2021-04-02

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US20210280688A1

公开(公告)日：2021-09-09

申请号：US17328674

申请日：2021-05-24

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Juntao LI ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US20210280674A1

公开(公告)日：2021-09-09

申请号：US17313700

申请日：2021-05-06

Applicant: Tessera, Inc.

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

公开(公告)号：US11062911B2

公开(公告)日：2021-07-13

申请号：US16796614

申请日：2020-02-20

Applicant: Tessera, Inc.

Inventor： Fee Li Lie ,  Dongbing Shao ,  Robert Wong ,  Yongan Xu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L29/78

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US20210210380A1

公开(公告)日：2021-07-08

申请号：US17212267

申请日：2021-03-25

Applicant: Tessera, Inc.

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.