公开(公告)号：US11342230B2

公开(公告)日：2022-05-24

申请号：US16505063

申请日：2019-07-08

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3115

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

公开(公告)号：US11121233B2

公开(公告)日：2021-09-14

申请号：US16391622

申请日：2019-04-23

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Julien Frougier ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/78 ,  H01L29/165

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

公开(公告)号：US20210111032A1

公开(公告)日：2021-04-15

申请号：US17087185

申请日：2020-11-02

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng

IPC: H01L21/308 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/265 ,  H01L21/426 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/786

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

公开(公告)号：US10607991B2

公开(公告)日：2020-03-31

申请号：US16002590

申请日：2018-06-07

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

公开(公告)号：US11380589B2

公开(公告)日：2022-07-05

申请号：US16662845

申请日：2019-10-24

Applicant: TESSERA, INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

公开(公告)号：US11276612B2

公开(公告)日：2022-03-15

申请号：US16681347

申请日：2019-11-12

Applicant: TESSERA, INC.

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

公开(公告)号：US20210399114A1

公开(公告)日：2021-12-23

申请号：US17465135

申请日：2021-09-02

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Julien Frougier ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/311 ,  H01L29/775

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

公开(公告)号：US20210280688A1

公开(公告)日：2021-09-09

申请号：US17328674

申请日：2021-05-24

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Juntao LI ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US11049953B2

公开(公告)日：2021-06-29

申请号：US16939415

申请日：2020-07-27

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US11043581B2

公开(公告)日：2021-06-22

申请号：US16798079

申请日：2020-02-21

Applicant: Tessera, Inc.

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/762 ,  H01L29/775 ,  H01L29/786 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.