公开(公告)号：US11094824B2

公开(公告)日：2021-08-17

申请号：US16685329

申请日：2019-11-15

Applicant: TESSERA, INC.

Inventor： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K Kanakasabapathy ,  Peng Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/324

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

公开(公告)号：US10727315B2

公开(公告)日：2020-07-28

申请号：US16252663

申请日：2019-01-20

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US10593802B2

公开(公告)日：2020-03-17

申请号：US15629280

申请日：2017-06-21

Applicant: TESSERA, INC.

Inventor： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC: H01L21/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/324

Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

公开(公告)号：US11342230B2

公开(公告)日：2022-05-24

申请号：US16505063

申请日：2019-07-08

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3115

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

公开(公告)号：US11276612B2

公开(公告)日：2022-03-15

申请号：US16681347

申请日：2019-11-12

Applicant: TESSERA, INC.

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

公开(公告)号：US20210280688A1

公开(公告)日：2021-09-09

申请号：US17328674

申请日：2021-05-24

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Juntao LI ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US11049953B2

公开(公告)日：2021-06-29

申请号：US16939415

申请日：2020-07-27

Applicant: Tessera, Inc.

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US10854753B2

公开(公告)日：2020-12-01

申请号：US16238193

申请日：2019-01-02

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Peng Xu

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a fin region including fins formed from the substrate, at least one fin cut region formed in the substrate adjacent to the fin region and having a different depth in the substrate than the fin region, and shallow trench isolation regions having substantially a same height in the fin cut regions and the fin region.

公开(公告)号：US20220157666A1

公开(公告)日：2022-05-19

申请号：US17592470

申请日：2022-02-03

Applicant: Tessera, Inc.

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

公开(公告)号：US20220069118A1

公开(公告)日：2022-03-03

申请号：US17511134

申请日：2021-10-26

Applicant: Tessera, Inc.

Inventor： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/324

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.