公开(公告)号：US11004933B2

公开(公告)日：2021-05-11

申请号：US16042498

申请日：2018-07-23

Applicant: TESSERA, INC.

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

公开(公告)号：US10658461B2

公开(公告)日：2020-05-19

申请号：US16042388

申请日：2018-07-23

Applicant: TESSERA, INC.

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.

公开(公告)号：US20210280674A1

公开(公告)日：2021-09-09

申请号：US17313700

申请日：2021-05-06

Applicant: Tessera, Inc.

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.