公开(公告)号：US11257717B2

公开(公告)日：2022-02-22

申请号：US17093351

申请日：2020-11-09

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US10832952B2

公开(公告)日：2020-11-10

申请号：US16014025

申请日：2018-06-21

Applicant: TESSERA, INC.

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US20210210380A1

公开(公告)日：2021-07-08

申请号：US17212267

申请日：2021-03-25

Applicant: Tessera, Inc.

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

公开(公告)号：US10985056B2

公开(公告)日：2021-04-20

申请号：US15852151

申请日：2017-12-22

Applicant: TESSERA, INC.

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

公开(公告)号：US10957584B2

公开(公告)日：2021-03-23

申请号：US15852176

申请日：2017-12-22

Applicant: TESSERA, INC.

Inventor： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

公开(公告)号：US20220181205A1

公开(公告)日：2022-06-09

申请号：US17571814

申请日：2022-01-10

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US20210082758A1

公开(公告)日：2021-03-18

申请号：US17093351

申请日：2020-11-09

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.