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    SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
    1.
    发明申请
    SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA 有权

    公开(公告)号：US20220181205A1

    公开(公告)日：2022-06-09

    申请号：US17571814

    申请日：2022-01-10

    Applicant: Tessera, Inc.

    Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee ,  Theodorus E. Standaert

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

    SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
    2.
    发明申请
    SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA 有权

    公开(公告)号：US20210082758A1

    公开(公告)日：2021-03-18

    申请号：US17093351

    申请日：2020-11-09

    Applicant: Tessera, Inc.

    Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

    Selective recessing to form a fully aligned via
    4.
    发明授权
    Selective recessing to form a fully aligned via 有权

    公开(公告)号：US10832952B2

    公开(公告)日：2020-11-10

    申请号：US16014025

    申请日：2018-06-21

    Applicant: TESSERA, INC.

    Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

    Low aspect ratio interconnect
    5.
    发明授权
    Low aspect ratio interconnect 审中-公开

    公开(公告)号：US10672707B2

    公开(公告)日：2020-06-02

    申请号：US16250351

    申请日：2019-01-17

    Applicant: TESSERA, INC.

    Inventor： Benjamin D. Briggs ,  Elbert E. Huang ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  David L. Rath ,  Chih-Chao Yang

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

    Selective recessing to form a fully aligned via
    6.
    发明授权
    Selective recessing to form a fully aligned via 有权

    公开(公告)号：US11257717B2

    公开(公告)日：2022-02-22

    申请号：US17093351

    申请日：2020-11-09

    Applicant: Tessera, Inc.

    Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert E. Huang ,  Joe Lee ,  Theodorus E. Standaert

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

    SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS
    7.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS 有权

    公开(公告)号：US20210043563A1

    公开(公告)日：2021-02-11

    申请号：US17068230

    申请日：2020-10-12

    Applicant: Tessera, Inc.

    Inventor： Benjamin D. Briggs ,  Takeshi Nogami ,  Raghuveer R. Patlolla

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

    LOW ASPECT RATIO INTERCONNECT
    8.
    发明申请
    LOW ASPECT RATIO INTERCONNECT 审中-公开

    公开(公告)号：US20200328156A1

    公开(公告)日：2020-10-15

    申请号：US16888245

    申请日：2020-05-29

    Applicant: Tessera, Inc.

    Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  David L. Rath ,  Chih-Chao Yang

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

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