公开(公告)号：US10964588B2

公开(公告)日：2021-03-30

申请号：US16868475

申请日：2020-05-06

Applicant: Tessera, Inc.

Inventor： Christopher J. Penny ,  Benjamin David Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US10651078B2

公开(公告)日：2020-05-12

申请号：US16406115

申请日：2019-05-08

Applicant: TESSERA, INC.

Inventor： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US20210335706A1

公开(公告)日：2021-10-28

申请号：US17341112

申请日：2021-06-07

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

公开(公告)号：US20210217653A1

公开(公告)日：2021-07-15

申请号：US17215314

申请日：2021-03-29

Applicant: Tessera, Inc.

Inventor： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US11056429B2

公开(公告)日：2021-07-06

申请号：US16817491

申请日：2020-03-12

Applicant: Tessera, Inc.

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.