公开(公告)号：US20210280422A1

公开(公告)日：2021-09-09

申请号：US17328569

申请日：2021-05-24

Applicant: Tessera, Inc.

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3213

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US11056429B2

公开(公告)日：2021-07-06

申请号：US16817491

申请日：2020-03-12

Applicant: Tessera, Inc.

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

公开(公告)号：US11018007B2

公开(公告)日：2021-05-25

申请号：US16675630

申请日：2019-11-06

Applicant: TESSERA, INC.

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/31 ,  H01L21/027 ,  H01L45/00 ,  H01L21/28 ,  H01L51/00

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US20210335706A1

公开(公告)日：2021-10-28

申请号：US17341112

申请日：2021-06-07

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

公开(公告)号：US10741449B2

公开(公告)日：2020-08-11

申请号：US16114816

申请日：2018-08-28

Applicant: TESSERA, INC.

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John Zhang

IPC: H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/306 ,  H01L29/78

Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.

公开(公告)号：US20210202313A1

公开(公告)日：2021-07-01

申请号：US17181399

申请日：2021-02-22

Applicant: Tessera, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US10964588B2

公开(公告)日：2021-03-30

申请号：US16868475

申请日：2020-05-06

Applicant: Tessera, Inc.

Inventor： Christopher J. Penny ,  Benjamin David Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US10651078B2

公开(公告)日：2020-05-12

申请号：US16406115

申请日：2019-05-08

Applicant: TESSERA, INC.

Inventor： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US20210217653A1

公开(公告)日：2021-07-15

申请号：US17215314

申请日：2021-03-29

Applicant: Tessera, Inc.

Inventor： Christopher J. Penny ,  Benjamin D. Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L23/528

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

公开(公告)号：US10930553B2

公开(公告)日：2021-02-23

申请号：US16257221

申请日：2019-01-25

Applicant: TESSERA, INC.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.