Invention Grant
- Patent Title: Stacked transistors with different channel widths
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Application No.: US16114816Application Date: 2018-08-28
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Publication No.: US10741449B2Publication Date: 2020-08-11
- Inventor: Kangguo Cheng , Lawrence A. Clevenger , Balasubramanian S. Pranatharthiharan , John Zhang
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/786 ; H01L21/02 ; H01L29/775 ; H01L29/66 ; H01L29/423 ; H01L29/40 ; H01L29/08 ; H01L29/06 ; H01L27/088 ; H01L21/306 ; H01L29/78
Abstract:
A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
Public/Granted literature
- US20190013244A1 STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS Public/Granted day:2019-01-10
Information query
IPC分类:
