公开(公告)号：US20200152628A1

公开(公告)日：2020-05-14

申请号：US16738569

申请日：2020-01-09

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US20210305247A1

公开(公告)日：2021-09-30

申请号：US17221401

申请日：2021-04-02

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US10998314B2

公开(公告)日：2021-05-04

申请号：US16738569

申请日：2020-01-09

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US10665589B2

公开(公告)日：2020-05-26

申请号：US16054417

申请日：2018-08-03

Applicant: TESSERA, INC.

Inventor： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC: H01L27/088 ,  H01L29/66 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

公开(公告)号：US11342446B2

公开(公告)日：2022-05-24

申请号：US16684115

申请日：2019-11-14

Applicant: TESSERA, INC.

Inventor： Michael A. Guillorn ,  Terence B. Hook ,  Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/10

Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.