Invention Grant
- Patent Title: Nanosheet field effect transistors with partial inside spacers
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Application No.: US16684115Application Date: 2019-11-14
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Publication No.: US11342446B2Publication Date: 2022-05-24
- Inventor: Michael A. Guillorn , Terence B. Hook , Robert R. Robison , Reinaldo A. Vega , Rajasekhar Venigalla
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: TESSERA, INC.
- Current Assignee: TESSERA, INC.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/28 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L29/786 ; B82Y10/00 ; H01L29/775 ; H01L29/10
Abstract:
A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
Public/Granted literature
- US20200098893A1 NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS Public/Granted day:2020-03-26
Information query
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