公开(公告)号：US20250167100A1

公开(公告)日：2025-05-22

申请号：US18917885

申请日：2024-10-16

Applicant: STMicroelectronics International N.V.

Inventor： Cristiano Gianluca STELLA

IPC: H01L23/52 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

Abstract: Packaged electronic device, having a C-shaped leadframe including a base section and a pair of transverse sections extending transversely to the base section. A first die and a second die have a first contact region at a first main surface and a second contact region at the second main surface; the first main surfaces of the first and the second dice are attached to a first face of the base section of the leadframe. A first lead is coupled to the second contact region of the first die and has a first external contact portion. A second lead is coupled to the second contact region of the second die and has a second external contact portion. A packaging mass surrounds the leadframe, the first lead and the second lead, embeds the first and the second dice and extends level with the base section and with the transverse sections of the leadframe as well as with the external contact portions of the leads.

公开(公告)号：US20250159906A1

公开(公告)日：2025-05-15

申请号：US18935091

申请日：2024-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Alain OSTROVSKY ,  Jerome DUBOIS ,  Latifa DESVOIVRES ,  Simon JEANNOT ,  Christian BOCCACCIO

IPC: H10B63/00 ,  H10B63/10 ,  H10N70/00 ,  H10N70/20

Abstract: A method manufactures a memory including at least one first phase-change memory cell, each first cell including a resistive element, a first metal layer, and a second layer made of a phase-change material, the first layer being located between the resistive element and the second layer. The method includes the forming of a level including the resistive element, the forming of a third metal layer on the level, the etching of the third layer, and then the forming of the second layer.

公开(公告)号：US20250158617A1

公开(公告)日：2025-05-15

申请号：US18938809

申请日：2024-11-06

Applicant: STMicroelectronics International N.V.

Inventor： Dorde CVEJANOVIC

IPC: H03K19/17736 ,  H03K19/0185 ,  H03K19/20

Abstract: A clock signal detection circuit includes a first input that receives an always-on clock signal, and a second input that receives an activatable clock signal. A detection flip-flop circuit has a data input terminal that receives an always-high logic signal, a clock terminal that receives the always-on clock signal, a reset terminal that receives a reset signal, and a data output terminal that produces an asynchronous clock detection signal. The reset signal is asserted to reset the detection flip-flop circuit in response to the activatable clock signal being asserted, and the reset signal is de-asserted to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted. The asynchronous clock detection signal is passed to an output to provide a clock detection signal that is asserted to indicate that the activatable clock signal is absent.

公开(公告)号：US20250157898A1

公开(公告)日：2025-05-15

申请号：US18389257

申请日：2023-11-14

Applicant: STMicroelectronics International N.V.

Inventor： Venero SANTAMARIA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A leadframe includes first leads and second leads, wherein each lead of the first and second leads has an upper surface. First and second silver spots are provided on the upper surface of each lead of the first and second leads. An integrated circuit die has a front surface including first and second interconnection pads. A first pillar is mounted to each first interconnection pad, and second pillar is mounted to each second interconnection pad. The integrated circuit die is mounted in flip chip orientation to the leadframe with the first pillars soldered to the first silver spots and the second pillars soldered to the second silver spots. A resin body encapsulates the integrated circuit die mounted to the leadframe.

公开(公告)号：US20250157860A1

公开(公告)日：2025-05-15

申请号：US18388571

申请日：2023-11-10

Applicant: STMicroelectronics International N.V.

Inventor： Alberto PAGANI ,  Mattia DE NICOLA

IPC: H01L21/66

Abstract: Wafer level testing is performed on a wafer including integrated circuit dies, each integrated circuit die including a die pads, with each die pad covered by a protection layer. The wafer level testing includes, at a given die pad: puncturing through the protection layer with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad; performing a first electrical test of the integrated circuit die through the probe; horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.

公开(公告)号：US12299444B2

公开(公告)日：2025-05-13

申请号：US18323049

申请日：2023-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Sofiane Landi

IPC: G06F9/30 ,  G06F9/345

Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.

公开(公告)号：US20250151269A1

公开(公告)日：2025-05-08

申请号：US18933452

申请日：2024-10-31

Applicant: STMicroelectronics International N.V.

Inventor： Madjid AKBAL ,  Franck MELUL ,  Arnaud REGNIER ,  Francesco LA ROSA

IPC: H10B41/30 ,  H01L29/423 ,  H10B41/10

Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.

公开(公告)号：US20250147764A1

公开(公告)日：2025-05-08

申请号：US18913223

申请日：2024-10-11

Applicant: STMicroelectronics International N.V.

Inventor： Philippe Pijourlet ,  Brice Dufour

IPC: G06F9/35 ,  G06F9/30 ,  G06F13/12

Abstract: The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access.

公开(公告)号：US20250146159A1

公开(公告)日：2025-05-08

申请号：US18933194

申请日：2024-10-31

Applicant: STMicroelectronics International N.V.

Inventor： Paolo CREMA

IPC: C25D5/48 ,  C25D3/38 ,  C25D3/46 ,  C25D5/10 ,  C25D7/12 ,  C25D17/00

Abstract: Articles carried by a carrier are processed in a sequence of processing steps that includes a plating step where a base layer of plating material is plated on a surface of the carrier. The plating material plated on the surface of the carrier is selectively stripped to partially remove the plating material to reduce e thickness of the base layer of plating material plated present on the surface of the carrier. A residual protective layer of plating material having the reduced thickness is left on the surface of the carrier.

公开(公告)号：US20250145451A1

公开(公告)日：2025-05-08

申请号：US18929345

申请日：2024-10-28

Applicant: STMicroelectronics International N.V.

Inventor： Gabriele GATTERE ,  Manuel RIANI

IPC: B81B3/00 ,  B81C1/00

Abstract: A microelectromechanical device includes: a supporting body, containing semiconductor material; a movable mass, constrained to the supporting body with a relative degree of freedom with respect to a first motion direction perpendicular to the supporting body; and at least one stopping structure, configured to limit out-of-plane movements of the movable mass along the first motion direction. The stopping structure includes: first elements, extending parallel to the first motion direction and anchoring the stopping structure to the supporting body; and a second element, extending transversally to the first elements, surmounting and connecting the first elements.