公开(公告)号：US20250151269A1

公开(公告)日：2025-05-08

申请号：US18933452

申请日：2024-10-31

Applicant: STMicroelectronics International N.V.

Inventor： Madjid AKBAL ,  Franck MELUL ,  Arnaud REGNIER ,  Francesco LA ROSA

IPC: H10B41/30 ,  H01L29/423 ,  H10B41/10

Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.