公开(公告)号：US20240404595A1

公开(公告)日：2024-12-05

申请号：US18676630

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

公开(公告)号：US20250151269A1

公开(公告)日：2025-05-08

申请号：US18933452

申请日：2024-10-31

Applicant: STMicroelectronics International N.V.

Inventor： Madjid AKBAL ,  Franck MELUL ,  Arnaud REGNIER ,  Francesco LA ROSA

IPC: H10B41/30 ,  H01L29/423 ,  H10B41/10

Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.

公开(公告)号：US20240404596A1

公开(公告)日：2024-12-05

申请号：US18676719

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.