公开(公告)号：US20250147764A1

公开(公告)日：2025-05-08

申请号：US18913223

申请日：2024-10-11

Applicant: STMicroelectronics International N.V.

Inventor： Philippe Pijourlet ,  Brice Dufour

IPC: G06F9/35 ,  G06F9/30 ,  G06F13/12

Abstract: The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access.