公开(公告)号：US20250158617A1

公开(公告)日：2025-05-15

申请号：US18938809

申请日：2024-11-06

Applicant: STMicroelectronics International N.V.

Inventor： Dorde CVEJANOVIC

IPC: H03K19/17736 ,  H03K19/0185 ,  H03K19/20

Abstract: A clock signal detection circuit includes a first input that receives an always-on clock signal, and a second input that receives an activatable clock signal. A detection flip-flop circuit has a data input terminal that receives an always-high logic signal, a clock terminal that receives the always-on clock signal, a reset terminal that receives a reset signal, and a data output terminal that produces an asynchronous clock detection signal. The reset signal is asserted to reset the detection flip-flop circuit in response to the activatable clock signal being asserted, and the reset signal is de-asserted to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted. The asynchronous clock detection signal is passed to an output to provide a clock detection signal that is asserted to indicate that the activatable clock signal is absent.