公开(公告)号：US20250157860A1

公开(公告)日：2025-05-15

申请号：US18388571

申请日：2023-11-10

Applicant: STMicroelectronics International N.V.

Inventor： Alberto PAGANI ,  Mattia DE NICOLA

IPC: H01L21/66

Abstract: Wafer level testing is performed on a wafer including integrated circuit dies, each integrated circuit die including a die pads, with each die pad covered by a protection layer. The wafer level testing includes, at a given die pad: puncturing through the protection layer with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad; performing a first electrical test of the integrated circuit die through the probe; horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.