公开(公告)号：US12009426B2

公开(公告)日：2024-06-11

申请号：US17827457

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/94 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/062

CPC分类号： H01L29/7848 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/66545 ,  Y02E10/50

摘要： The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

公开(公告)号：US11949000B2

公开(公告)日：2024-04-02

申请号：US17874286

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  I-Shan Huang

IPC分类号： H01L31/062 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/7851

摘要： A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

公开(公告)号：US11935892B2

公开(公告)日：2024-03-19

申请号：US17862305

申请日：2022-07-11

申请人： Intel Corporation

发明人： Sairam Subramanian ,  Walid M. Hafez

IPC分类号： H01L29/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/0924 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US11804564B2

公开(公告)日：2023-10-31

申请号：US17737908

申请日：2022-05-05

申请人： Jinko Solar Co., Ltd.

发明人： Jiahua Qu ,  Jingsheng Jin ,  Linan Zhang

IPC分类号： H01L31/049 ,  H01L31/0312 ,  H01L31/18 ,  H01L31/062

CPC分类号： H01L31/049 ,  H01L31/0312 ,  H01L31/1876 ,  H01L31/062

摘要： Provided is a solar cell, including: an N-type semiconductor substrate having a front surface and a rear surface opposite to the front surface; a boron diffusion layer arranged on the front surface of the N-type semiconductor substrate, a first passivation layer is provided on a surface of the boron diffusion layer, and a first electrode is provided passing through the first passivation layer to form an electrical connection with the N-type semiconductor substrate; and a phosphorus-doped polysilicon layer arranged on the rear surface of the N-type semiconductor substrate. A silicon oxide layer containing nitrogen and phosphorus is provided between the rear surface of the N-type semiconductor substrate and the phosphorus-doped polysilicon layer, a second passivation layer is provided on a surface of the phosphorus-doped polysilicon layer, and a second electrode is provided passing through the second passivation layer to form an electrical connection with the phosphorus-doped polysilicon layer.

公开(公告)号：US11791386B2

公开(公告)日：2023-10-17

申请号：US17895054

申请日：2022-08-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC分类号： H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/404 ,  H01L27/088 ,  H01L29/7816

摘要： A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US11626326B2

公开(公告)日：2023-04-11

申请号：US17166548

申请日：2021-02-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin ,  Che-Ming Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

摘要： A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

公开(公告)号：US11522073B2

公开(公告)日：2022-12-06

申请号：US17081877

申请日：2020-10-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Chen-Ping Chen ,  Kuei-Yu Kao ,  Hsiao Wen Lee

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

公开(公告)号：US11410873B2

公开(公告)日：2022-08-09

申请号：US16953567

申请日：2020-11-20

申请人： Applied Materials, Inc.

发明人： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

IPC分类号： H01L29/00 ,  H01L29/94 ,  H01L31/062 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

摘要： Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

公开(公告)号：US11380779B2

公开(公告)日：2022-07-05

申请号：US17060049

申请日：2020-09-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

发明人： Feng Han ,  Lei Shi ,  Hung-Chih Tsai ,  Liang-Yu Su ,  Hang Fan

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

摘要： A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

公开(公告)号：US11328961B2

公开(公告)日：2022-05-10

申请号：US16626352

申请日：2019-11-21

申请人： SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.

发明人： Huafei Xie

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L21/8238 ,  H01L29/06

摘要： A method of manufacturing an inverter and an inverter are provided. The method of manufacturing the inverter includes following steps: forming a substrate and forming a first insulating layer on the substrate; forming a semiconductor-type carbon nanotube film on the first insulating layer; patterning the semiconductor-type carbon nanotube film to form a first active layer and a second active layer arranged at an interval; forming a first barrier layer on the first active layer and forming a second barrier layer on the second active layer, wherein the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donor film layer; and forming a first source and a first drain which are in contact with and spaced apart from two ends of the first active layer and forming a second source and a second drain which are in contact with and spaced with two ends of the second active layer, wherein the first drain is connected to the second source. By using the semiconductor-type carbon nanotube as the active layer to cooperate with the electrophilic film layer and the electron donor film layer as a barrier layer, manufacturing process of the inverter can be simplified, and manufacturing cost of the inverter can be reduced.