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公开(公告)号：US11908903B2
公开(公告)日：2024-02-20
申请号：US17370750
申请日：2021-07-08
发明人： Kuei-Yu Kao , Shih-Yao Lin , Chen-Ping Chen , Chih-Han Lin , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/40 , H01L29/66 , H01L29/06 , H01L29/423
CPC分类号： H01L29/401 , H01L29/0665 , H01L29/42392 , H01L29/66484 , H01L29/66545
摘要： A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.
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公开(公告)号：US11522073B2
公开(公告)日：2022-12-06
申请号：US17081877
申请日：2020-10-27
发明人： Shih-Yao Lin , Chih-Han Lin , Chen-Ping Chen , Kuei-Yu Kao , Hsiao Wen Lee
IPC分类号： H01L31/062 , H01L31/113 , H01L29/66 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/78
摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
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公开(公告)号：US20220130978A1
公开(公告)日：2022-04-28
申请号：US17081877
申请日：2020-10-27
发明人： Shih-Yao Lin , Chih-Han Lin , Chen-Ping Chen , Kuei-Yu Kao , Hsiao Wen Lee
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78 , H01L27/088 , H01L21/8234
摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
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公开(公告)号：US11721741B2
公开(公告)日：2023-08-08
申请号：US17224509
申请日：2021-04-07
IPC分类号： H01L29/49 , H01L29/78 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/786 , H01L21/28 , H01L29/423
CPC分类号： H01L29/4983 , H01L21/28123 , H01L29/0673 , H01L29/0847 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
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公开(公告)号：US12034056B2
公开(公告)日：2024-07-09
申请号：US17371907
申请日：2021-07-09
发明人： Shih-Yao Lin , Kuei-Yu Kao , Chen-Ping Chen , Chih-Chung Chiu , Chih-Han Lin , Ming-Ching Chiang , Chao-Cheng Chen
IPC分类号： H01L29/00 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/786
CPC分类号： H01L29/4908 , H01L21/0259 , H01L29/0665 , H01L29/42392 , H01L29/4983 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78696
摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.
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公开(公告)号：US20230009347A1
公开(公告)日：2023-01-12
申请号：US17371907
申请日：2021-07-09
发明人： Shih-Yao Lin , Kuei-Yu Kao , Chen-Ping Chen , Chih-Chung Chiu , Chih-Han Lin , Ming-Ching Chiang , Chao-Cheng Chen
IPC分类号： H01L29/49 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
摘要： A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion. The lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a first layer and a second layer. The first layer is in contact with a first portion of the sidewall and the second layer is in contact with a second portion of the sidewall.
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公开(公告)号：US20220328646A1
公开(公告)日：2022-10-13
申请号：US17224509
申请日：2021-04-07
IPC分类号： H01L29/49 , H01L29/78 , H01L29/08 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/28 , H01L29/66
摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
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