公开(公告)号：US11569129B2

公开(公告)日：2023-01-31

申请号：US16918177

申请日：2020-07-01

Applicant: DISCO CORPORATION

Inventor： Jinyan Zhao ,  Yoshiaki Yodo

IPC: B23K26/38 ,  H01L21/301 ,  H01L21/78 ,  B23K26/53 ,  B23K26/57 ,  H01L21/268 ,  H01L21/683 ,  B23K26/18 ,  B23K103/00

Abstract: A workpiece processing method includes holding a workpiece unit on a holding table and forming a division start point. The workpiece unit has a workpiece having a front side and a back side, and an additional member formed on the back side of the workpiece. The additional member is different in material from the workpiece. The workpiece unit is held on the holding table with the additional member opposed to the holding table. The division start point is formed by applying a laser beam to the front side of the workpiece with the focal point of the laser beam set inside the workpiece. The laser beam forms a modified layer inside the workpiece and simultaneously forming a division start point inside the additional member due to the leakage of the laser beam from the focal point toward the back side of the workpiece.

公开(公告)号：US11502042B2

公开(公告)日：2022-11-15

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US10950498B2

公开(公告)日：2021-03-16

申请号：US16583749

申请日：2019-09-26

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Srinivas Gandikota ,  Pramit Manna ,  Abhijit Basu Mallick

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532 ,  H01L21/311

Abstract: Methods of dep-etch in semiconductor devices (e.g. V-NAND) are described. A metal layer is deposited in a feature. The metal layer is removed by low temperature atomic layer etching by oxidizing the surface of the metal layer and etching the oxide in a layer-by-layer fashion. After removal of the metal layer, the features are filled with a metal.

公开(公告)号：US10134598B2

公开(公告)日：2018-11-20

申请号：US15321245

申请日：2014-10-10

Applicant: Mitsubishi Electric Corporation

Inventor： Kazunari Nakata ,  Tamio Matsumura ,  Yoshiaki Terasaki

IPC: H01L23/48 ,  H01L21/02 ,  B24D3/00 ,  H01L21/301 ,  B24B1/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/683 ,  H01L21/66 ,  B24B27/00 ,  B24B49/12 ,  B24B7/22

Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).

公开(公告)号：US09831380B2

公开(公告)日：2017-11-28

申请号：US14752632

申请日：2015-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Kyu Park ,  Wan Jong Kim ,  Young Geun Jun

IPC: H01L21/48 ,  H01L21/301 ,  H01L21/304 ,  H01L21/78 ,  H01L23/495 ,  H01L41/338 ,  H01L33/00 ,  H01L23/00

CPC classification number: H01L33/0095 ,  H01L21/4842 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor device package includes: forming a based frame provided with an outer frame, a plurality of unit frames spaced apart from the outer frame by separating grooves interposed therebetween, and a first connector and a second connector forming connections between each of the plurality of unit frames and the outer frame; forming a package body in each of the plurality of unit frames to allow a mounting area of each unit frame to be open; removing one of the first connector and second the connector connected to each unit frame; mounting a semiconductor device in the mounting area of the unit frame; and cutting the other of the first connector and second the connector connected to each unit frame and separating, from the base frame, the unit frame in which the package body is formed.

公开(公告)号：US09679855B1

公开(公告)日：2017-06-13

申请号：US15082954

申请日：2016-03-28

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Jon Aday

IPC: H01L23/544 ,  H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/3178 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/11

Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, that is configured with trenches that are dry-etched into a surface of the substrate inside an area defined by scribe lines of the substrate. A crack stop structure is provided for the semiconductor device that includes a polymer dielectric layer coating that fills the trenches with a polymer dielectric material and provides a dielectric layer over the surface of the substrate inside the area. The polymer dielectric layer coating and trenches are configured to reduce cracking or chipping of the substrate in the area defined by scribe lines after cutting.

公开(公告)号：US09601475B2

公开(公告)日：2017-03-21

申请号：US15041127

申请日：2016-02-11

Applicant: Intel Deutschland GmbH

Inventor： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC: H01L21/301 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/60 ,  H01L23/00 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

公开(公告)号：US09548431B2

公开(公告)日：2017-01-17

申请号：US15044577

申请日：2016-02-16

Applicant: Masato Toita ,  Jianfeng Chen ,  Yuxin Li ,  Yuting Wang ,  Hironori Ishii ,  Ken Kitamura

Inventor： Masato Toita ,  Jianfeng Chen ,  Yuxin Li ,  Yuting Wang ,  Hironori Ishii ,  Ken Kitamura

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L33/56 ,  H01L33/58 ,  H01L33/48 ,  H01L33/62 ,  H01L33/44 ,  H01L33/54

CPC classification number: A61L2/10 ,  H01L33/44 ,  H01L33/483 ,  H01L33/486 ,  H01L33/54 ,  H01L33/56 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2924/1815 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00014

Abstract: In various embodiments, an illumination device features an ultraviolet (UV) light-emitting device at least partially surrounded by an encapsulant and having a rigid lens. Downward forces is applied while the encapsulant is at least partially cured to substantially prevent partial or full detachment of the rigid lens from the light-emitting device, and/or substantially suppress formation of bubbles between the light-emitting device and the rigid lens.

Abstract translation: 在各种实施例中，照明装置具有至少部分地由密封剂包围并具有刚性透镜的紫外（UV）发光装置。 施加向下的力，同时密封剂至少部分固化，以基本上防止刚性透镜从发光装置的部分或全部脱离，和/或基本上抑制在发光装置和刚性透镜之间形成气泡。

公开(公告)号：US09437458B2

公开(公告)日：2016-09-06

申请号：US14077742

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Nee Wan Khoo ,  Vigneswaran Letcheemana

IPC: H01L21/304 ,  H01L21/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/301 ,  H01L21/48 ,  B23K26/36 ,  B23K26/40 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/78 ,  B23K26/361 ,  B23K26/362 ,  B23K26/40 ,  B23K26/402 ,  B23K2101/40 ,  B23K2103/166 ,  B23K2103/50 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L22/14 ,  H01L24/97 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles and covering the unit lead frames with a molding compound after the semiconductor dies are attached to the die paddles. Spaced apart cuts are formed in the periphery of each unit lead frame that sever the leads from the periphery of each unit lead frame and extend at least partially into the molding compound in regions of the periphery where the leads are located so that the molding compound remains intact between the cuts. The lead frame strip is processed after the cuts are formed, and the unit lead frames are later separated into individual packages.

Abstract translation: 引线框架条包括多个连接的单元引线框架，每个单元引线框架具有管芯焊盘和连接到单元引线框架的外围的多个引线。 通过在将半导体管芯附接到管芯焊盘上之后，通过将半导体管芯附接到每个管芯焊盘并且用模制化合物覆盖单元引线框架来处理引线框架条。 在每个单元引线框架的周边形成间隔开的切口，其从每个单元引线框架的周边切断引线，并且在引线所在的周边的区域中至少部分地延伸到模制化合物中，使得模制化合物保持 切割之间完好无损。 在形成切口之后处理引线框条，然后将单元引线框架分离成单个封装。

公开(公告)号：US08900925B2

公开(公告)日：2014-12-02

申请号：US13921362

申请日：2013-06-19

Applicant: Richard Spitz ,  Alfred Goerlach ,  Robert Kolb

Inventor： Richard Spitz ,  Alfred Goerlach ,  Robert Kolb

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/00 ,  H01L21/76 ,  H01L21/30 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L29/861 ,  H01L29/66 ,  H01L29/32

CPC classification number: H01L29/6609 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/861

Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.

Abstract translation: 在制造二极管的方法中，使用半导体晶体晶片来生产跨越半导体晶体晶片的顶侧以平面方式延伸的p-n或n-p结。 分离边缘垂直于半导体晶体晶片的顶侧形成，其边缘延伸穿过p-n或n-p结。 实现半导体晶体晶片的分离，其中从干扰开始，通过局部加热和半导体晶体晶片的局部冷却传播裂缝。 如此形成的分离裂隙沿着半导体晶体的晶面延伸，这避免了p-n或n-p结区域的缺陷的形成。